1. Field of the Invention
The invention relates to a process flow to obtain low temperature sidewall oxidation for W/WN/Poly-gatestack semiconductor structures. The process utilizes temperatures far below the currently used 1050xc2x0 C. temperature via anodic oxidation, thereby providing less outdiffusion of implants near the surface, and allows more margin in small groundrule device design for support devices, such as buried p-FET.
2. Description of Related Art
A conventional polycide gate stack in a DRAM device may include a gate electrode stack, which is referred to by the acronym GC. This GC may consists of the following composite sequence of layers:
Silicon/gate oxide/N+ doped polysilicon/WSix/cap-insulator, where the patterned N+ doped polysilicon and WSix layers comprise the gate conductor (GC) in the gate electrode stack.
The fabrication of the polycide structure generally consist of an in-situ doped polysilicon deposition, or polysilicon deposition followed by implantation of As+ or P+, followed by a cleaning and tungsten (WSix) deposition. However, one problem encountered during fabrication employing a post GC stack heat cycle step is that dopant atoms in the polysilicon migrate into the WSix layer. When the dopant is distributed and accumulates at the polysilicon/WSix and WSix/cap silicon nitride interfaces, this migration and pile-up of dopant reduces the dopant concentration at the polysilicon/gate oxide interface and causes a partially depleted gate that degrades the FET performance by increasing the equivalent oxide thickness.
U.S. Pat. No. 5,923,999 discloses a process of preventing migration of dopant atoms from a polysilicon layer into the WSix layer in post gate conductor (GC) heat cycles. The method forms a stable dopant diffusion barrier in a polysilicon/WSix structure to minimize outdiffusion of dopant from the polysilicon layer into the WSix layer. The diffusion barrier prevents depletion of dopants in polysilicon during post-WSix deposition annealing, and insures that a high concentration of electrically active dopant material remains at the polysilicon/gate oxide interface to avoid an increase in the equivalent oxide thickness and the associated degradation in the MOSFET performance.
A process for manufacturing DRAMs using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow is disclosed in U.S. Pat. No. 5,716,862. The semiconductor manufacturing process for forming insulated transistor gates Is accomplished by performing a temperature controlled insulation step wherein the temperature range is between 600-957xc2x0 C. to form polygate sidewall oxidation about the vertical sidewalls of the p-channel transistor gate electrodes, followed by performing a ptype impurity implant into the n-well regions.
There is a need for a low temperature sidewall oxidation for a W/WN/poly-gate stack to prevent out diffusion of dopant implants near the surface and to allow more margin in device design for support devices, such as buried p-FET, when preparing semiconductors.
One object of the present invention is to provide a process flow in semiconductor processing of a W/WN/poly gate stack to provide low temperature sidewall oxidation for the gate stack to obtain less outdiffusion of implants near the surface and to thereby allow more margin in small groundrule device design for support devices, such as buried p-FET.
A further object of the present invention is to provide, in a process flow for preparing semiconductor devices comprising a W/WN/poly gate stack to utilize a sidewall oxidation temperature less than about 1050xc2x0 C. in view of the need for temperature constraints that are more stringent at present because of the lack of margin in small groundrule device design existing at present.
A yet further object of the present invention is to provide, in a process flow for preparing a semiconductor comprising a W/WN/poly-gate stack, to allow a low temperature sidewall oxidation of the gatestack to obtain less outdiffusion of dopant implants near the surface by utilizing low temperatures for sidewall oxidation employing anodic oxidation.
In general, the process flow for preparing the low temperature gate sidewall oxidation GC stack (W/WN/poly and cap SiN) semiconductor device is prepared by:
1. Utilizing total GC lithography, where the GC total is a combination of: PORGC lithography and connecting all of the GC features, with no etch bead removal;
2. Employing a conventional POR etch;
3. Connecting all GC features with large structures;
4. Covering the wafer with photoresist;
5. Performing etch bead removal;
6. Affecting a mask opening to enable contacting W at the wafer edge(3 mm) with an anode;
7. Performing anodic oxidationxe2x80x94putting the gate stack on positive and the counter electrode on negative potential (weak acid)xe2x80x94the anode is formed via metal ring press contactxe2x80x94and ensuring that the anode is not in contact with the acid (no HF containing material)xe2x80x94all connected W/WN/Poly stack has sidewall oxidexe2x80x94the chosen acid determining the ratio. between oxide thickness on the poly and W;
8. Opening up the GCs in the array and supports;
9. Using a second GC mask to separate the GC lines;
10. Utilizing a best case MUV
11. Utilizing a worst case second DUV; and
12. Employing a second GC etch that also removes sidewall oxide.